Course - Analog CMOS 1 - TFE4187
TFE4187 - Analog CMOS 1
About
Examination arrangement
Examination arrangement: School exam
Grade: Letter grades
| Evaluation | Weighting | Duration | Grade deviation | Examination aids |
|---|---|---|---|---|
| School exam | 100/100 | 4 hours | D |
Course content
Frequency response, amplifier topologies, feedback, noise analysis, opertaional amplifiers, comparators, sample-and-hold circuits. Use of the SPICE simulation program.
Learning outcome
The course aims to provide a thorough understanding of design of analog integrated circuits in CMOS and an overview of fundamental building blocks in analog CMOS.
Knowledge: The candidate has - in depth understanding of the theoretical framework for design of analog integrated circuits - in-depth understand techniques used for sustainable design of analog CMOS integrated circuits - detailed knowledge of professional software tools used for design of analog CMOS circuits
Skills: The candidate can - combine earlier acquired knowledge and skills in math and electronics together with new theory to solve practical challenges in design of analog CMOS circuits - use professional software tools for design and simulation of analog CMOS circuits - design analog CMOS circuits
General competence: - present the results of the design project
Learning methods and activities
Lectures. Assignments, both theoretical and computer based. Mandatory term project and assignments. The course may be held in English.
Compulsory assignments
- Exercises
Further on evaluation
Written exam only given in English. If there is a re-sit examination, in August, the examination form may be changed from written to oral.
Recommended previous knowledge
Transistor theory, small signal equivalent circuits for MOS and BJT, general circuit analysis techniques, control systems theory, s-domain analysis.
Course materials
Announced at course start.
Credit reductions
| Course code | Reduction | From | To |
|---|---|---|---|
| TFE4200 | 7.5 | AUTUMN 2012 |
No
Version: 1
Credits:
7.5 SP
Study level: Second degree level
Term no.: 1
Teaching semester: AUTUMN 2024
Language of instruction: English
Location: Trondheim
- Technological subjects
Department with academic responsibility
Department of Electronic Systems
Examination
Examination arrangement: School exam
- Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
- Autumn ORD School exam 100/100 D 2024-12-04 15:00 INSPERA
-
Room Building Number of candidates SL430 Sluppenvegen 14 30 - Summer UTS School exam 100/100 D INSPERA
-
Room Building Number of candidates
- * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.
For more information regarding registration for examination and examination procedures, see "Innsida - Exams"