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TFE4171

Design of Digital Systems 2

Choose study year
Credits 7.5
Level Second degree level
Course start Spring 2025
Duration 1 semester
Language of instruction English
Location Trondheim
Examination arrangement Aggregate score

About

About the course

Course content

This course deals with the challenges when developing complex digital systems such as a System-on-Chip (SoC). Focus is on advanced methods, notations and languages, tools and systems, high level (abstract) description and communication, simulation, and verification including UVM (Universal Verification Methodology). Verification will receive the highest focus.

Subjects are System On Chip as definition and the challenges in developing such, and also the system decription languages used for that purpose. For verification, both high level description and assertion based verification in SystemVerilog and UVM, and also formal verification with model checking is used.

Term project: The use of high level design tools for description, simulation, verification and implementation.

Learning outcome

Knowledge: The candidate has

  • detailed understanding of what characterizes systems-on-chip, how such are specified, designed, implemented and used, and what challenges lies within this.
  • advanced knowledge about high level descriptions of complex systems containing both hardware and software.
  • profound understanding of the principles in formal and assertion based verification.
  • detailed knowledge about the fundamentals and methods for modelling and simulation on system and transaction level.

Skills: The candidate can

  • use high level description languages for the design of modules for systems-on-chip or other complex system of hardware and software.
  • develop assertion based properties and use such for system level verification.
  • describe temporal logic system requirements and prove or disprove such by model checking.

Learning methods and activities

Lectures. Practical/theoretical exercises, and a term project in groups. All laboratory exercises are mandatory and have to be approved for entrance to the exam.

Compulsory assignments

  • Laboratory exercises

Further on evaluation

The total grade in the subject is based on a combination of the exam, counting 75 % towards the final grade, and the project report, counting 25 %.

If there is a re-sit examination in August, the examination form may be changed from written to oral. If the course is to be repeated a later year, both the exam and the project report have to be repeated, while the obligatory laboratory exercises will be accepted up to three years after they have been approved.

Required previous knowledge

The student needs to know and be able to use at least one hardware description language such as VHDL or Verilog for register level modeling.

Course materials

Will be announced at course start.

Credit reductions

Course code Reduction From
TFE4170 7.5 sp Autumn 2014
FE8129 7.5 sp Autumn 2014
TFE4175 3.7 sp Autumn 2014
FE8803 3.7 sp Autumn 2014
FE8128 3.7 sp Autumn 2014
SIE4075 3.7 sp Autumn 2014
This course has academic overlap with the courses in the table above. If you take overlapping courses, you will receive a credit reduction in the course where you have the lowest grade. If the grades are the same, the reduction will be applied to the course completed most recently.

Subject areas

  • Electronics
  • Applied Electrical Engineering
  • Electrical Power Engineering
  • Technological subjects

Contact information

Course coordinator

Lecturers

Department with academic responsibility

Department of Electronic Systems