Course content

Advanced topics in processor microarchitecture. Detailed discussion and implementation of simple pipelined CPUs. Introduction to the design and analysis of Instruction Set Architectures (ISAs). In-depth review of out-of-order execution, branch prediction, speculative execution, and performance modeling. Introduction to memory system design and performance modeling.

Learning outcome

Knowledge:

• The student should have a thorough understanding of the construction and mode of operation of pipelined processors.
• The student should have a theoretical understanding of advanced performance improvement techniques for scalar processor cores including out-of-order execution, branch prediction, and speculative execution.
• The student should have a basic understanding of analytical performance models for out-of-order processors.
• The student should understand important trade-offs regarding instruction set design.
• The student should have a basic understanding of memory system design.

Skills:

• The student should be able to implement optimised pipelined processors with a hardware description language.
• The student should be able to evaluate computer architecture optimisations with a quantitative approach.

General competence:

• The student should be proficient in computer design and be able to use this knowledge in projects at all levels of abstraction.

Learning methods and activities

Auditorium lectures, self-study. Compulsory laboratory exercises. Compulsory theory exercises. In-class problem solving. All teaching will be in English.

Compulsory assignments

• Compulsory theoretical and practical exercises

Recommended previous knowledge

TDT4160 Computers and Digital Design, or equivalent.

Course materials

John L. Hennessy and David A. Patterson: "Computer Architecture - A Quantitative Approach, 6th Edition", Morgan Kaufmann Publishers. Other relevant texts will be announced at the start of the semester. All teaching materials will be in English.

Credit reductions