Magnus Själander

About

Magnus Själander is a Professor at the Department of Computer Science and has been a Visiting Senior Lecturer at the Department of Information Technology, Uppsala University (2016-2021). He is the coordinator of the Energy Efficient Computing Systems (EECS) strategic research initiative at NTNU and the head of the Computing unit at the Department of Computer Science, NTNU. Själander has an M.Sc. from Luleå University of Technology, a Ph.D. from Chalmers University of Technology, and a Docent from Uppsala University. Before joining NTNU, Själander worked as a Digital Design Engineer at Aeroflex Gaisler (2008-2009) and as a researcher at NXP Semiconductors (2007), Florida State University (2012-2013), and Uppsala University (2014-2015). Själander's research focuses on the design (compilers, architecture, and hardware implementation) of secure, high-performance, and energy-efficient systems at all scales. Själander is a senior member of ACM and IEEE, as well as member of the HiPEAC European Network of Excellence. Själander is an Associate Editor of the Journal of Parallel and Distributed Computing (JPDC).

Selected Publications

See the Google Scholar profile for complete list of publications.

Power Efficiency

M. Själander, M. Martonosi, and S. Kaxiras, "Power-Efficient Computer Architectures: Recent Advances", Synthesis Lectures on Computer Architecture, Morgan & Claypool, Dec. 2014. ISBN: 978-1-62705-645-8.

B. Goel, S. A. McKee, and M. Själander, "Techniques to Measurement, Model, and Manage Power", Advances in Computers, Green and Sustainable Computing: Part I vol. 87, Nov. 2012. ISBN: 978-0-12-396528-8

Secure Speculative Execution

P. Aimoniotis, A. Kvalsvik, M. Själander, and S. Kaxiras, "ReCon: Efficient Detection, Management, and Use of Non-Speculative Information Leakage" Proceedings of the ACM/IEEE International Symposium on Microarchitecture (MICRO), October 2023.

A. Kvalsvik, P. Aimoniotis, S. Kaxiras, and M. Själander, "Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes", Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2023.

C. Sakalis, S. Kaxiras, and M. Själander, "Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks", ACM Transactions on Architecture and Code Optimization (TACO), vol. 20, no. 1, pp. 1-24, Mar. 2023.

P. Aimoniotis, C. Sakalis, M. Själander, and S. Kaxiras, "Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions", IEEE Computer Architecture Letters (CAL), vol. 20, no. 2, pp. 162-165, 2021.

P. Aimoniotis, A. Kvalsvik, M. Själander, and S. Kaxiras, "Data-Out Instruction-In (DOIN!): Leveraging Inclusive Caches to Attack Speculative Delay Schemes", IEEE International Symposium on Secure and Private Execution Environment Design (SEED), vol. 32, pp. 49-60, Sep. 2022.

K.-A. Tran, C. Sakalis, M. Själander, A. Ros, S.Kaxiras, and A. Jimborean, "Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design", Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct. 2020.

C. Sakalis, S. Kaxiras, A. Ros, A. Jimborean, and M. Själander, "Understanding Selective Delay as a Method for Efficient Secure Speculative Execution", IEEE Transactions on Computers (TC), Aug. 2020.

C. Sakalis, S.Kaxiras, A. Ros, A. Jimborean, and M. Själander, "Efficient Invisible Speculative Execution through Selective Delay and Value Prediction", Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA), June 2019.

C. Sakalis, M. Alipour, A. Ros, A. Jimborean, S. Kaxiras, and M. Själander, "Ghost loads: what is the cost of invisible speculation?", Proceedings of the ACM International Conference on Computing Frontiers (CF), pp. 153-163, May 2019.

Bit-serial Matrix-matrix Multiplication

D. Metz, V. Kumar, and M. Själander, "BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers", ACM Transactions on Embedded Computing Systems (TECS), 2023.

Y. Umuroglu, C. Davide, L. Rasnayake, T. B Preusser, and M. Själander, "Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 12, no. 3, pp. 1-24, Aug. 2019.

Y. Umuroglu, L. Rasnayake, and M. Själander, "BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing", Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications (FPL), Aug. 2018.

Instruction Scheduling

K.-A. Tran, A. Jimborean, T. Carlson, K. Koukos, M. Själander, and S. Kaxiras, "SWOOP: Software-Hardware Co-Design for Non-Speculative, Execute-Ahead, In-Order Cores", Proceedings of the ACM International Conference on Programming Language Design and Implementation (PLDI), pp. 328-343, June 2018.

K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoilos, S. Kaxiras, and A. Jimborean, "Clairvoyance: Look-Ahead Compile-time Scheduling", Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO), pp. 171-184, 4-8 Feb. 2017.

K.-A. Tran, T. Carlson, K. Koukos, M. Själander, V. Spiliopoulos, S. Kaxiras, and A. Jimborean, "Static Instruction Scheduling for High Performance on Limited Hardware", IEEE Transactions on Computers (TC), vol. 67, no. 4, pp. 513-527, Nov. 2017.

B. Davis, P. Gavin, R. Baird, M. Själander, I. Finlayson, F. Rasapour, G. Cook, G.-R. Uh, D. Whalley and G. Tyson, "Scheduling Instruction Effects for a Statically Pipelined Processor", Proceedings of the International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES), pp. 167-176, 4-9 Oct. 2015.

M. Thuresson, M. Själander, M. Björk, L. Svensson, P. Larsson-Edefors, and P. Stenström, "FlexCore: Utilizing Exposed Datapath Control for Efficient Computing", Journal of Signal Processing Systems, vol. 57, no. 1, pp. 5-19, Oct. 2009.

Task Scheduling

R. Nishtala, V. Petrucci, P. M. Carpenter, and M. Själander, "Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services", Proceedings of the ACM International Conference on High-Performance Computer Architecture (HPCA), Feb. 2020.

M. Själander, A. Terechko, M. Duranton, "A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures", Proceedings of Euromicro Conference on Digital System Design: Architectures, Methods, and Tools (DSD), pp. 149-157, 3-5 Sep. 2008.

Optimizing Compilers

N. Reissmann, J. C. Meyer, H. Bahmann, and M. Själander, "RVSDG: An Intermediate Representation for Optimizing Compilers", ACM Transactions on Embedded Computing Systems (TECS), Mar. 2020.

Cache Optimizations

A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors, "Designing a Practical Data Filter Cache to Improve Both Energy Efficiency and Performance", ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, pp. 54:1--54:25, Dec. 2013.

P. Gavin, D. Whalley, and M. Själander, "Reducing Instruction Fetch Energy in Multi-Issue Processors", ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, pp. 64:1--64:24, Dec. 2013.

A. Bardizbanyan, M. Själander, D. Whalley, and P. Larsson-Edefors, "Speculative Tag Access for Reduced Energy Dissipation in Set-Associative L1 Data Caches", Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 302-308, 6-9 Oct. 2013.

Multiplier Design

T. Hoang-Thanh, M. Själander, and P. Larsson-Edefors, "High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit", IEEE Transactions on Circuits and Systems, I: Regular papers, Invited for SOCC Special Issue (TCAS-I), vol. 57, no. 12, pp. 3073-3081, Dec. 2010

M. Själander, and P. Larsson-Edefors, "Multiplication Acceleration through Twin Precision", IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 17, no. 9, pp. 1233-1246, Sep. 2009.

H. Eriksson, P. Larsson-Edefors, M. Sheeran, M. Själander, D. Johansson, M. Schölin, "Multiplier Reduction Tree with Logarithmic Logic Depth and Regular Connectivity", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4-8, 21-24 May 2006.

Research

Själander's research focuses on the design of high-performance and energy-efficient systems at all scales. His background lies primarily in computer architecture and circuit design, and he has led implementation projects in both FPGA and ASIC technologies. Recent projects focus increasingly on hardware/software co-design and efficient low-power systems (compiler, architecture, and hardware implementation) for high-efficiency computing. The driving philosophy behind these projects is that by extracting more information from the application and by monitoring the system, we can better control the hardware to use resources more efficiently in terms of performance, power, and area.

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

BISMO is a programmable FPGA accelerator for low-precision integer matrix multiplication. It offers high-performance matrix multiplication, which is beneficial for applications like quantized neural network inference and approximate computing approaches.

SOCRATES: Self-Organizing Computational substRATES

SOCRATES (Self-Organizing Computational substRATES) is a long-term time horizon project seeking radical breakthroughs toward efficient and powerful data analysis available everywhere, from the simplest sensor node to the most complex supercomputer.

SpinENGINE: Harnessing the Emergent Properties of Nanomagnet Ensembles for Massively Parallel Data Analysis

The SpinENGINE project will lay the foundations for a new, massively parallel, platform based on emergent behavior in nanomagnet ensembles.

Publications

See the Google Scholar profile for a complete list of articles.

List of VLSI Related Conferences.

List of Computer Architecture Related Conferences.

2024

Chakraborty, Shounak; Saha, Sangeet; Själander, Hans Magnus; McDonald-Maier, Klaus D.. (2024) MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Agarwal, Sukarn; Chakraborty, Shounak; Själander, Hans Magnus. (2024) TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)
Academic article

2023

Saha, Sangeet; Chakraborty, Shounak; Agarwal, Sukarn; Gangopadhyay, Rahul; Själander, Magnus; McDonald-Maier, Klaus. (2023) DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Transactions on Parallel and Distributed Systems
Academic article
Kvalsvik, Amund Bergland; Aimoniotis, Pavlos; Kaxiras, Stefanos; Själander, Hans Magnus. (2023) Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Metz, David Christoph; Kumar, Vineet; Själander, Hans Magnus. (2023) BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. ACM Transactions on Embedded Computing Systems
Academic article

2022

Sakalis, Christos; Kaxiras, Stefanos; Själander, Hans Magnus. (2022) Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. ACM Transactions on Architecture and Code Optimization (TACO)
Academic article
Jensen, Johannes Høydahl; Strømberg, Anders; Lykkebø, Odd Rune Strømmen; Penty, Arthur George; Lealiaert, Jonathan; Själander, Magnus. (2022) Flatspin: A large-scale artificial spin ice simulator. Physical review B (PRB)
Academic article

2021

Chakraborty, Shounak; Saha, Sangeet; Själander, Magnus; McDonald-Maier, Klaus. (2021) Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Transactions on Embedded Computing Systems
Academic article
Aimoniotis, Pavlos; Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) WIP: “It’s a Trap!”—How Speculation Invariance Can Be Abused with Forward Speculative Interference. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Sakalis, Christos; Chowdhury, Zamshed; Wadle, Shayne; Akturk, Ismail; Ros, Alberto; Själander, Magnus. (2021) Do Not Predict – Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Chakraborty, Shounak; Själander, Magnus. (2021) WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Transactions on Architecture and Code Optimization (TACO)
Academic article
Aimoniotis, Pavlos; Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. IEEE computer architecture letters
Academic article
Själander, Magnus. (2021) International Symposium on Secure and Private Execution Environment Design (SEED). IEEE (Institute of Electrical and Electronics Engineers) IEEE (Institute of Electrical and Electronics Engineers)
Academic anthology/Conference proceedings
Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper

2020

Jensen, Johannes Høydahl; Strømberg, Anders; Lykkebø, Odd Rune Strømmen; Penty, Arthur George; Själander, Magnus; Folven, Erik. (2020) flatspin: A Large-Scale Artificial Spin Ice Simulator. arXiv.org
Academic article
Reissmann, Nico; Meyer, Jan Christian; Bahmann, Helge; Själander, Magnus. (2020) RVSDG: An intermediate representation for optimizing compilers. ACM Transactions on Embedded Computing Systems
Academic article
Nishtala, Rajiv; Petrucci, Vinicius; Carpenter, Paul; Själander, Magnus. (2020) Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. IEEE Symposium on High-Performance Computer Architecture (HPCA)
Academic article
Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus. (2020) Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE transactions on computers
Academic article
Tran, Kim-Anh; Sakalis, Christos; Själander, Magnus; Ros, Alberto; Kaxiras, Stefanos; Jimborean, Alexandra. (2020) Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper

2019

Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Själander, Magnus. (2019) Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus. (2019) Efficient invisible speculative execution through selective delay and value prediction. Computer Architecture
Academic article
Sakalis, Christos; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus. (2019) Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. ACM Journal on Emerging Technologies in Computing Systems (JETC)
Academic article
Sakalis, Christos; Alipour, Mehdi; Ros, Alberto; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus. (2019) Ghost loads: what is the cost of invisible speculation?. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Umuroglu, Yaman; Conficconi, Davide; Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Preusser, Thomas B.; Själander, Magnus. (2019) Optimizing bit-serial matrix multiplication for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems
Academic article

2018

Umuroglu, Yaman; Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Själander, Magnus. (2018) BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Tran, Kim-anh; Jimborean, Alexandra; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Kaxiras, Stefanos. (2018) SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper

2017

Carlson, Trevor E.; Tran, Kim-anh; Jimborean, Alexandra; Koukos, Konstantinos; Själander, Magnus; Kaxiras, Stefanos. (2017) Transcending Hardware Limits with Software Out-of-order Processing. IEEE computer architecture letters
Academic article
Tran, Kim-anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos. (2017) Static Instruction Scheduling for High Performance on Limited Hardware. IEEE transactions on computers
Academic article
Tran, Kim-Anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos. (2017) Clairvoyance: Look-ahead compile-time scheduling. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper

2016

Moreau, Daniel; Bardizbanyan, Alen; Själander, Magnus; Whalley, David; Larsson-Edefors, Per. (2016) Practical Way Halting by Speculatively Accessing Halt Tags. IEEE conference proceedings
Academic chapter/article/Conference paper
Sanchez, Carlos; Gavin, Peter; Moreau, Daniel; Själander, Magnus; Whalley, David; Larsson-Edefors, Per. (2016) Redesigning a tagless access buffer to require minimal ISA changes. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Själander, Magnus; Borgström, Gustaf; Klymenko, Mykhailo V; Remacle, Françoise; Kaxiras, Stefanos. (2016) Techniques for Modulating Error Resilience in Emerging Multi-Value Technologies. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper

Journal publications

Agarwal, Sukarn; Chakraborty, Shounak; Själander, Hans Magnus. (2024) TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. Proceedings, International Parallel and Distributed Processing Symposium (IPDPS)
Academic article
Saha, Sangeet; Chakraborty, Shounak; Agarwal, Sukarn; Gangopadhyay, Rahul; Själander, Magnus; McDonald-Maier, Klaus. (2023) DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Transactions on Parallel and Distributed Systems
Academic article
Metz, David Christoph; Kumar, Vineet; Själander, Hans Magnus. (2023) BISDU: A Bit-Serial Dot-Product Unit for Microcontrollers. ACM Transactions on Embedded Computing Systems
Academic article
Sakalis, Christos; Kaxiras, Stefanos; Själander, Hans Magnus. (2022) Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks. ACM Transactions on Architecture and Code Optimization (TACO)
Academic article
Jensen, Johannes Høydahl; Strømberg, Anders; Lykkebø, Odd Rune Strømmen; Penty, Arthur George; Lealiaert, Jonathan; Själander, Magnus. (2022) Flatspin: A large-scale artificial spin ice simulator. Physical review B (PRB)
Academic article
Chakraborty, Shounak; Saha, Sangeet; Själander, Magnus; McDonald-Maier, Klaus. (2021) Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization. ACM Transactions on Embedded Computing Systems
Academic article
Chakraborty, Shounak; Själander, Magnus. (2021) WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption. ACM Transactions on Architecture and Code Optimization (TACO)
Academic article
Aimoniotis, Pavlos; Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. IEEE computer architecture letters
Academic article
Jensen, Johannes Høydahl; Strømberg, Anders; Lykkebø, Odd Rune Strømmen; Penty, Arthur George; Själander, Magnus; Folven, Erik. (2020) flatspin: A Large-Scale Artificial Spin Ice Simulator. arXiv.org
Academic article
Reissmann, Nico; Meyer, Jan Christian; Bahmann, Helge; Själander, Magnus. (2020) RVSDG: An intermediate representation for optimizing compilers. ACM Transactions on Embedded Computing Systems
Academic article
Nishtala, Rajiv; Petrucci, Vinicius; Carpenter, Paul; Själander, Magnus. (2020) Twig: Multi-Agent Task Management for Colocated Latency-Critical Cloud Services. IEEE Symposium on High-Performance Computer Architecture (HPCA)
Academic article
Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus. (2020) Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE transactions on computers
Academic article
Sakalis, Christos; Kaxiras, Stefanos; Ros, Alberto; Jimborean, Alexandra; Själander, Magnus. (2019) Efficient invisible speculative execution through selective delay and value prediction. Computer Architecture
Academic article
Sakalis, Christos; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus. (2019) Evaluating the Potential Applications of Quaternary Logic for Approximate Computing. ACM Journal on Emerging Technologies in Computing Systems (JETC)
Academic article
Umuroglu, Yaman; Conficconi, Davide; Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Preusser, Thomas B.; Själander, Magnus. (2019) Optimizing bit-serial matrix multiplication for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems
Academic article
Carlson, Trevor E.; Tran, Kim-anh; Jimborean, Alexandra; Koukos, Konstantinos; Själander, Magnus; Kaxiras, Stefanos. (2017) Transcending Hardware Limits with Software Out-of-order Processing. IEEE computer architecture letters
Academic article
Tran, Kim-anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos. (2017) Static Instruction Scheduling for High Performance on Limited Hardware. IEEE transactions on computers
Academic article

Books

Själander, Magnus. (2021) International Symposium on Secure and Private Execution Environment Design (SEED). IEEE (Institute of Electrical and Electronics Engineers) IEEE (Institute of Electrical and Electronics Engineers)
Academic anthology/Conference proceedings

Part of book/report

Chakraborty, Shounak; Saha, Sangeet; Själander, Hans Magnus; McDonald-Maier, Klaus D.. (2024) MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Kvalsvik, Amund Bergland; Aimoniotis, Pavlos; Kaxiras, Stefanos; Själander, Hans Magnus. (2023) Doppelganger Loads: A Safe, Complexity-Effective Optimization for Secure Speculation Schemes. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Aimoniotis, Pavlos; Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) WIP: “It’s a Trap!”—How Speculation Invariance Can Be Abused with Forward Speculative Interference. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Sakalis, Christos; Chowdhury, Zamshed; Wadle, Shayne; Akturk, Ismail; Ros, Alberto; Själander, Magnus. (2021) Do Not Predict – Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Sakalis, Christos; Själander, Magnus; Kaxiras, Stefanos. (2021) Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Tran, Kim-Anh; Sakalis, Christos; Själander, Magnus; Ros, Alberto; Kaxiras, Stefanos; Jimborean, Alexandra. (2020) Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Själander, Magnus. (2019) Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Sakalis, Christos; Alipour, Mehdi; Ros, Alberto; Jimborean, Alexandra; Kaxiras, Stefanos; Själander, Magnus. (2019) Ghost loads: what is the cost of invisible speculation?. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Umuroglu, Yaman; Sasnayake Mudiyanselage, Lahiru Kasun Rasnayake; Själander, Magnus. (2018) BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Tran, Kim-anh; Jimborean, Alexandra; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Kaxiras, Stefanos. (2018) SWOOP: Software-Hardware Co-design for Non-speculative, Execute-Ahead, In-Order Cores. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Tran, Kim-Anh; Carlson, Trevor E.; Koukos, Konstantinos; Själander, Magnus; Spiliopoulos, Vasileios; Kaxiras, Stefanos. (2017) Clairvoyance: Look-ahead compile-time scheduling. IEEE (Institute of Electrical and Electronics Engineers)
Academic chapter/article/Conference paper
Moreau, Daniel; Bardizbanyan, Alen; Själander, Magnus; Whalley, David; Larsson-Edefors, Per. (2016) Practical Way Halting by Speculatively Accessing Halt Tags. IEEE conference proceedings
Academic chapter/article/Conference paper
Sanchez, Carlos; Gavin, Peter; Moreau, Daniel; Själander, Magnus; Whalley, David; Larsson-Edefors, Per. (2016) Redesigning a tagless access buffer to require minimal ISA changes. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper
Själander, Magnus; Borgström, Gustaf; Klymenko, Mykhailo V; Remacle, Françoise; Kaxiras, Stefanos. (2016) Techniques for Modulating Error Resilience in Emerging Multi-Value Technologies. Association for Computing Machinery (ACM)
Academic chapter/article/Conference paper

Teaching

TDT4260 Computer Architecture, Examiner, 2016-Present
TDT01 Architecture of Computing Systems, Lecturer, 2018-Present
DT8123 Advanced Computing, Lecturer 2021-Present
TDT01 Architecture of Computing Systems, Examiner, 2017
TDT4258 Low-Level Programming, Coordinator, 2016-2017

Supervision

Postdocs

Shounak Chakraborty, NTNU, 2019-2024
Bart Iver van Blokland, NTNU, 2022-2023
Vineet Kumar, NTNU, 2022-2023
Rajiv Nishtala, NTNU, 2018-2020

Ph.D. students

Håvard Rognebakke Krogstie, main supervisor, NTNU 2024-present
Jacbo Odgård Tørring, main supervisor, NTNU 2024-present
Charalampos Bezaitis, main supervisor, NTNU, 2023-present
Muhammad Umer Khalid, co-supervisor with Prof. Snorre Aunet, 2023-present
Silvio Heverton Campelo de Santana, co-supervisor with Prof. Magnus Jahre, 2022-present
Roman Kaspar Brunner, co-supervisor with Prof. Rakesh Kumar, NTNU, 2022-present
David Metz, main supervisor, NTNU, 2020-present
Amund Bergland Kvalsvik, main supervisor, NTNU, 2020-present
Anders Knap Gaustad, main supervisor, NTNU, 2020-present
Halvard Hummel, co-supervisor with Prof. Magnus Lie Hetland, NTNU, 2020-present
Joseph Rogers, co-supervisor with Prof. Magnu Jahre, NTNU, 2020-present
Fatemeh Ghasemisoumeeh, co-supervisor with Prof. Magnus Jahre, NTNU 2020-2024
Truls Asheim, co-supervisor with Prof. Rakesh Kumar, NTNU, 2019-2024
Anders Strømberg, co-supervisor with Prof. Erik Folven, NTNU, 2019-2024
Lasse Agentoft Eggen, co-supervisor with Prof. Magnus Jahre, NTNU, 2020-2022
Chris Sakalis, "Rethinking Speculative Execution from a Security Perspective" main supervisor, Uppsala University, 2017-2021
Lahiru Rasnayake, main supervisor, NTNU, 2017-2021
Nico Reissmann, "Principles, Techniques, and Tools for Explicit and Automatic Parallelization", mentored, NTNU, 2017-2019
Alen Bardizbanyan, "Data Access Techniques for Enhanced Energy Efficiency and Performance in In-order Pipelines", co-supervisor with Prof. Per Larsson-Edefors, Chalmers, 2010-2013
Peter Gavin, "Instruction Caching in Multithreading Processors Using Guarantees", mentored with Prof. David Whalley, Chalmers and FSU, 2011-2013
Bhavishya Goel, "Measurement, Modeling, and Characterization for Energy-Efficient Computing", mentored with Docent Sally A. McKee, Chalmers, 2011-2012
Dmitry Knyaginin, "Towards Large-Capacity and Cost-Effective Main Memories", mentored with Docent Sally A. McKee, Chalmers, 2010-2012
Tung Hoang Thanh, "Multi-Mode Datapath Circuits for Flexible and Energy-Efficient Computing", mentored with Prof. Per Larsson-Edefors, Chalmers, 2008-2010

Supervised thesis projects on topics of hardware and software design and implementation

John Askeland Lauvdal, “ Investigating Speculative Side-Channel Protection”, NTNU, 2023
Marcus Stensby Young, “Improving Memory Scheduling on an Out-of-Order Processor”, NTNU, 2023
Halvor Bjørstda, “Implementing RVSDG as a dialect of MLIR”, NTNU, 2023
Vetle Harnes, “Exploring Efficient Accelerator-Core Integration Strategies: A Case Study
of BISMO in Chipyard’, NTNU, 2023
Anders Knap Guastad, “Modelling Inclusive Cache Hierarchies in Multi-core Systems”, NTNU, 2022
Amund Bergland Kvalsvik, “Investigating the Usefulness of Simulators and Prototypes as Research Tools”, NTNU, 2021
David Metz and Erling Jellum “Evaluating FIFO-based Instruction Scheduling Techniques using FPGAs”, NTNU, 2020
Khakim Akhunov, “Way-predictive instruction cache access in Rocket Chip processor with RISC-V ISA”, NTNU 2020
Valentin Plotkin, “Evaluation of an Efficient Data Filter Cache in a RISC-V core”, NTNU, 2020
Edgar Mo Vedvik, “Implementing a RISC and L1 Data Cache in Hardware to Evaluate DAGDA Energy Efficiency”, NTNU, 2019
Ludvig Jordet, “Creation of a Software Programmable Hardware Interface”, NTNU, 2019
Kristoffer Monsen, “Challenges in Constructing a RISC-V Computing Platform”, NTNU, 2019
Martin Gundersen, “Analyzing an FPGA Neural Network Accelerator Design for Implementation in an ASIC”, NTNU, 2019
Erlend Sveen, “Strict Memory Protection for Microcontrollers”, NTNU, 2019
Håvard Tollefsen, “Evaluating performance impact of performing computations on storage nodes”, NTNU, 2018
Salahuddin Asjad, “Energy Efficient Data Accesses”, NTNU, 2017
Henrik Grandin, “Impact of Approximate Data in Arithmetic Operations”, Uppsala University, 2015
Gustaf Borgström, “Approximate computing for emerging technologies”, Uppsala University, 2015
Vahid Saljooghi, “Development and Integration of Level-1 Cache RTL Model”, Chalmers, 2012
Kashan Khurshid Ansari, “Microcode Optimization in FlexCore Compiler”, Chalmers, 2012
Hao Li, “A Cilk implementation of LTE Base-Station Uplink on TILEPro64”, Chalmers, 2012
Recep Gökhan Aslan and Cemil Caglar Boke, “DAT095 Project Renewal - Implementation of MP3 Player on FPGA”, Chalmers, 2011
Nikita Frolov, “Bau: A Declarative Scheduling Library”, Chalmers, 2011
Johan Rydh, “Embedded Camera Remote Control”, Chalmers, 2011
Ulf Jälmbrant and Erik der Hagopian, “Improved configurability with FlexSoC For the purpose of design time scheduling for processor exploration”, Chalmers, 2009
Thomas Schilling, “Scheduling Techniques for FlexCore”, Chalmers, 2008
Abdifatah Farah, “Efficient Datapath Multipliers”, Chalmers, 2008
Jonas Karlsson, “A MIPS and NISC implementation”, Chalmers, 2008
Erik Ryman, “FlexCore implementation on FPGA”, Chalmers, 2007
Martin Brink and Kristian Eklund, “A Flexible FFT/DCT Engine Using the Twin-Precision Technique”, Chalmers, 2006
Jan Mårts and Tomas Carlqvist, “A Hardware Audio Decoder Using Flexible Datapaths”, Chalmers, 2006

Researcher Assistants

Amund Bergland Kvalsvik, NTNU, 2020
Fatemeh Ghasemisoumeeh, NTNU, 2018-2020
Carlos Sanchez, Florida State University, 2013-2014
Ryan Baird, Florida State University, 2013
Brandon Davis, Florida State University, 2012-2013

Språkvelger

Magnus Själander