course-details-portlet

TFE4141 - Design of Digital Systems 1

About

Examination arrangement

Examination arrangement: Aggregate score
Grade: Letter grades

Evaluation Weighting Duration Grade deviation Examination aids
Term assignment 25/100
School exam 75/100 4 hours C

Course content

The subject covers how complex digital circuits and systems are modeled and simulated using Hardware Description Languages (HDL). Register Transfer Level (RTL) descriptions adapted for correct synthesis to integrated circuits is emphasized. RTL design-methods for energy efficient circuits and for production test of digital circuits and systems are also covered. The course includes lab exercises and a term project with use of FPGA. The subject covers these thematic parts: Advanced use of HDL, automatic and manual synthesis of digital modules and components at RTL level, trade-offs between performance, power consumption, and other functional and non-functional properties. Within test, fault models, test-generation, fault simulation, design for testability, self-test, test quality and test standards are covered.

Learning outcome

Knowledge The candidate -understands how advanced properties of Hardware Description Languages may be utilized to design (model) digital circuits and systems. -understands how the functionality of digital circuits and systems may be verified using simulation and test-benches. -has specialized knowledge about methods for high-level and register level synthesis of digital circuits and systems. - has detailed understanding of design methods used to make digital components and systems energy efficient and testable. B. Skills: The candidate -can use state-of-the-art software to model digital circuits and systems using Hardware Description Languages. -can write test-benches for simulation and verification of digital circuits and systems. -can use state-of-the-art synthesis tools to optimize and translate high-level and register-level hardware descriptions to digital circuits and systems. -can design energy efficient and testable digital components and systems. C. General competence: The candidate -can cooperate in a group on solving a practical term project. -can present results from a term project in a project report.

Learning methods and activities

Lectures. Practical/theoretical exercises and a term project in groups of two or three students. All exercises are mandatory. The course will be given in English if any international students are registered.

Compulsory assignments

  • Obligatory assignments

Further on evaluation

If there is a re-sit examination in August, the examination form may be changed from written to oral.

If the course is retaken a later year, both the exam and the term project have to be repeated while obligatory exercises will be accepted up to three years after they have been approved. A previous year's term project may be approved by the department upon application.

Required previous knowledge

Good knowledge of Boolean algebra and design of combinatorial and sequential digital circuits. Familiarity with the use of register transfer level languages for digital hardware design.

Course materials

Will be given at the semester start.

More on the course

No

Facts

Version: 1
Credits:  7.5 SP
Study level: Second degree level

Coursework

Term no.: 1
Teaching semester:  AUTUMN 2024

Language of instruction: English, Norwegian

Location: Trondheim

Subject area(s)
  • Electronics
  • Electronics and Telecommunications
  • Computers
  • Electrical Power Engineering
  • Physical Electronics
  • Technological subjects
Contact information
Course coordinator: Lecturer(s):

Department with academic responsibility
Department of Electronic Systems

Timetable

List view
Calendar view

Examination

Examination arrangement: Aggregate score

Term Status code Evaluation Weighting Examination aids Date Time Examination system Room *
Autumn ORD School exam 75/100 C 2024-12-16 09:00 PAPIR
Room Building Number of candidates
SL120 Sluppenvegen 14 1
SL274 Sluppenvegen 14 1
Storhall del 2 Idrettssenteret (Dragvoll) 57
Autumn ORD Term assignment 25/100

Submission
2024-11-22


23:59

Room Building Number of candidates
Summer UTS School exam 75/100 C INSPERA
Room Building Number of candidates
  • * The location (room) for a written examination is published 3 days before examination date. If more than one room is listed, you will find your room at Studentweb.
Examination

For more information regarding registration for examination and examination procedures, see "Innsida - Exams"

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